1. Field of the Invention
This invention relates generally to semiconductor memory array architectures, and, more particularly, to a semiconductor memory array architecture in which certain address decoding is divided into at least two parts to decrease the amount of space required for decoding lines and increase the amount of space available for data input/output lines.
2. Description of the Related Art
A semiconductor memory, for example, a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), typically comprises an array of memory cells, address decoding circuitry for selecting one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. In many cases, the array of memory cells will be sub-divided into several sub-arrays, or subsets of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (224 bits) of storage capacity, may be divided into 64 sub-arrays, each having 256K (218) memory cells. FIG. 1 illustrates a portion 10 of a memory array. The portion 10 includes a sub-array 11 of memory cells that may include, for example, 256K memory cells. Row decoding circuitry 12 receives row address signals and, based on those signals, activates a selected row 13 in the sub-array 11. Column decoding circuitry 14 receives column address signals and, based on those signals, selects a particular column 15 in the sub-array 11. By selecting a specific row 13 and specific column 15, a particular memory cell may be accessed so that its contents may be read or so that data may be written into it. Input/output lines 16 convey data signals between the sub-array 11 and other parts of the memory array for ultimate transmission to or from outside the memory array.
As illustrated in FIG. 1, the row decoding circuitry 12 is arranged along one edge of the sub-array 11, while the column decoding circuitry 14 is arranged along an adjacent edge of the sub-array 11. The row decoding circuitry 12 drives the rows 13 which span the sub-array 11 in a direction perpendicular to the edge of the sub-array 11 along which the row decoding circuitry 12 is arranged. In the same manner, the column decoding circuitry 14 selects the columns 15, and the columns 15 span the sub-array 11 in a direction perpendicular to the edge of the sub-array 11 along which the column decoding circuitry 14 is arranged. The input/output lines 16 are situated parallel to the rows 13, and the input/output lines 16 exit the sub-array 11 over the row decoding circuitry 12. The architecture illustrated in FIG. 1 may use a two layer metal semiconductor process in which the input/output lines 16 are formed in the first metal layer and the column decoding circuitry 12 is formed on the second metal layer.
FIG. 2 shows an alternative architecture for a semiconductor memory. A portion of a memory array 20 will include sub-arrays 21 and 22. Row decoding circuitry 23A-23D is arranged along opposing ends of each of the sub-arrays 21 and 22. Column decoding circuitry 24B is arranged between the sub-arrays 21 and 22, and the column address signals are coupled to the column decoding circuitry 24B by lines 26. Additional column decoding circuitry 24A and 24C is arranged along edges of the sub-arrays 21 and 22 opposing the edge along which the column decoding circuitry 24B is located. The column decoding circuitry 24B may be shared between the sub-arrays 21 and 22, the circuitry 24A may be shared between the sub-array 21 and a next adjacent sub-array, and the circuitry 24C may be shared between the sub-array 22 and a next adjacent sub-array. Sense amplifier circuitry 25A-25D is arranged alongside the column decoding circuitry 25A-25D and the sub-arrays 21 and 22. Each of the sub-arrays 21 and 22 has associated with it sense amplifier pull-down circuitry 25A and 25C, respectively, and sense amplifier pull-up circuitry 25B and 25D, respectively. In the architecture illustrated in FIG. 2, the complete sense amplifier for the sub-array 21 includes active pull-up devices in the circuitry 25B as well as active pull-down devices in the circuitry 25A. Input/output lines 27 are coupled to the sense amplifier circuitry 25A-25D and are routed to the periphery of the memory device.
As memory array architectures grow wider in terms of input/output lines, the testability, repair planes, and the size of the input/output routes themselves become a difficult problem to overcome. The amount of space required to accommodate the ever-growing number of input/output lines has become relatively large. Enlarging the semiconductor memory chip to accommodate the added space required for the growing number of input/output lines is an undesirable solution.
The present invention involves a semiconductor memory device having a first sub-array, the first sub-array including a first plurality of memory cells coupled to row lines and column lines, wherein the row lines are positioned substantially orthogonal to the column lines. Row address decode circuitry is coupled to the row lines and is adapted to select and activate at least one of the row lines. First column select lines are positioned substantially parallel to the row lines, and first column address decode circuitry is coupled to the first column select lines and is adapted to select a subset of the column lines. Second column address decode circuitry is positioned proximate an end of the column lines and is adapted to select at least one column line from the subset of column lines. Input/output lines are positioned substantially parallel to the column lines. The semiconductor memory device may also include a second sub-array having a second plurality of memory cells coupled to row lines and column lines. Second column select lines may be positioned substantially parallel to the row lines in the second sub-array. Third column address decode circuitry is coupled to the second column select lines and is adapted to select a subset of the second column lines. The second column address decode circuitry is adapted to select at least one column line from one of the subsets of the first column lines and second column lines.
In another aspect of the present invention, a semiconductor memory device comprises first and second sub-arrays, each sub-array having a plurality of memory cells coupled to row lines and column lines in a sub-array. First and second row address decode circuitry is coupled to the first and second sub-arrays, respectively, and is adapted to select at least one row line in the respective sub-arrays. First column address decode circuitry is coupled to first column select lines, the first column select lines being situated substantially parallel to the row lines in the first sub-array. The first column address decode circuitry is adapted to select a plurality of column lines in the first sub-array. Second column address decode circuitry is coupled to second column select lines, the second column select lines being situated substantially parallel to the row lines in the second sub-array. The second column address decode circuitry is adapted to select a plurality of column lines in the second sub-array. Third column address decode circuitry is coupled to third column select lines and is adapted to select at least one of the plurality of column lines selected by one of the first and second column decoding circuitry. Input/output lines are situated substantially parallel to the column lines in the first and second sub-arrays and are adapted to transmit data signals from at least one memory cell in one of the first and second sub-arrays. The semiconductor memory device may also include a plurality of sense amplifiers, wherein each sense amplifier is coupled to a column line in the first sub-array and to a column line in the second sub-array.